In a microprocessor or other electronics device within a computer system, various logic circuits, such as processing cores, may request data from other logic circuits within or outside of the microprocessor or computer system, which may be stored, at least temporarily, within the requesting logic circuit's cache memory for the logic circuit to use. Accordingly, requesting logic circuits and other electronic devices may be referred to as “cache agents”.
FIG. 1 illustrates a prior art portion of an architecture for translating and carrying out a memory request from a cache agent to a memory or input/output (I/O) device located somewhere within the computer system. The processor agent 101 of FIG. 1 may initiate a memory access operation, such as a write or read operation, by generating a logical address. The logical address is subsequently translated into a physical address. Translation between a logical address and a physical one may be performed according to a table, programmed by an operating system (OS), the entries of which map logical addresses to corresponding physical addresses. One such table is sometimes referred to as a “page table”. A “translation look-aside buffer” (TLB) 105 is a structure where page table entries are cached in the processor core where the translation occurs. Other translation mechanisms can also be used, including logic that takes a logical address and decodes a physical address according to some algorithm.
Each page table entry contains a physical address to which the logical address may be mapped. Furthermore, each entry may correspond to a group of physical addresses, such as a “page”, the size of which can be defined by the particular computer or processor architecture. Associated with each page table entry held in the TLB illustrated in FIG. 1 is a page attribute, which defines how the particular page of memory to which the entry corresponds is to be accessed. For example, a page may have associated therewith a number of attributes, such as “write back” (WB), which indicates that programming accesses to corresponding portions of physical memory could be cached, “write coalescing” (WC), which indicates that programming accesses to corresponding portions of physical memory are non-temporal (i.e. do not need to be cached), and that multiple writes can be coalesced/combined into a single for optimization, and “uncacheable” (UC), meaning that data accessed from the corresponding portions of physical memory cannot be cached or coalesced. Other physical memory attributes may also exist within each page table entry.
TLB page attributes are typically assigned to each page of physical memory mapped within the TLB by the OS associated with the particular processor in which the TLB exists. Unfortunately, other system memory attributes may be defined by the firmware that may or may not exactly correspond one-to-one with the attributes defined by the OS. For example, address decoder 110 may assign a system memory attribute to each physical address based, at least in part, on the firmware of the particular computer system. Because these attributes exist in different levels of system abstraction, page attributes for the higher OS level, and the memory attribute on the lower firmware or system level, these attributes are aliased to one another in an allowable set of cross-products defined in the system architecture of the processor. For example, some physical memory pages may be deemed “coherent”, meaning that accesses to that portion of memory may be only accessed according to a cache coherence protocol implemented through hardware within the processor or system, whereas other physical memory pages may be deemed “non-coherent”, meaning that accesses to that portion of memory need not be made coherent through hardware, and that a programmer may or may not choose a software method to maintain coherency.
Therefore, the TLB page attributes for a particular address may be assigned to a memory attribute by the address decoder. In many cases, the memory attributes correspond well to the TLB page attributes. For example, typically the address decoder will assign a “coherent” memory attribute to a physical address having a WB page attribute and “non-coherent” memory attribute to physical addresses having a WC or UC page attribute, which may be compatible attribute assignments in many cases. In the not-so-typical case that a memory attribute is assigned to a physical address that is inconsistent with the TLB page attribute (e.g., a non-coherent memory attribute assigned to a physical address page corresponding to a WB page attribute), the access will have to be repeated and the memory attribute corrected in one embodiment.
Once the memory attribute has been determined for a physical address, the address and memory attribute may be passed to a source request in-flight table, such as a missing address file (MAF) 115. The MAF, among other things, may determine availability of resources to be accessed by the physical address. Furthermore, the MAF may be responsible for issuing the address to the target device on the interconnect 120 in accordance with a specific protocol, such as a cache coherency protocol.
Typically, the physical memory attributes assigned by the address decoder require access to a look-up table, which may require multiple processor cycles to complete, thereby delaying the completion of the memory access generated by the cache agent.